Presentation | 2006-05-12 An Implementation of a Ternary-valued Logic Simulator using a Value-independent Simulator Kernel Takatomi WADA, Yasushi HIBINO, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In multi-valued logic, the expression by a little number of digits can be possible. So the integration of LSI is improved by the reduction in the number of wiring etc. Moreover, efficient processing that uses ternary-valued logic in the encryption processing is possible. We implement ternary-valued logic simulator needed in designing ternary-valued logical circuit. A value-independent kernel was used to improve the extendibility in implementation. Logic that uses an arbitrary ternary-valued expression can be simulated by setting the conversion of external expression into internal expression. And a flexible extension of the simulator is possible by adding the definition of the logic function used outside of the kernel. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | ternary-valued logic / logic simulation |
Paper # | VLD2006-8 |
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Committee | VLD |
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Conference Date | 2006/5/5(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | VLSI Design Technologies (VLD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | An Implementation of a Ternary-valued Logic Simulator using a Value-independent Simulator Kernel |
Sub Title (in English) | |
Keyword(1) | ternary-valued logic |
Keyword(2) | logic simulation |
1st Author's Name | Takatomi WADA |
1st Author's Affiliation | School of Information Science, Japan Advanced Institute of Science and Technology(JAIST)() |
2nd Author's Name | Yasushi HIBINO |
2nd Author's Affiliation | School of Information Science, Japan Advanced Institute of Science and Technology(JAIST) |
Date | 2006-05-12 |
Paper # | VLD2006-8 |
Volume (vol) | vol.106 |
Number (no) | 32 |
Page | pp.pp.- |
#Pages | 6 |
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