Presentation 2006-05-26
A 80/100MS/s 76.3/70.1-dB SNDR △Σ ADC for Digital TV Receivers
Yoshihisa FUJIMOTO, Yusuke KANAZAWA, Pascal LORE, Masayuki MIYAMOTO,
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Abstract(in English) A 4th-order switched-capacitor ΔΣ ADC with a 4-bits quantizer is designed for a low-power direct-conversion receiver for Japanese ISDB-T and European DVB-T. It, achieves a 76.3/70.1-dB SNDR over a 3.2/4-MHz bandwidth with a clock frequency of 80/100 MHz. The 1.7-mm^2 chip, fabricated in a 0.18μm CMOS process draws 13.2/19.1mA from a 1.8-V supply. It has a FOM of 0.7/1.64 pJ/conversion [1].
Keyword(in Japanese) (See Japanese page)
Keyword(in English) △Σ ADC / △Σ modulator / ISDB-T / DVB-T / digital TV / double sampling
Paper # ICD2006-31
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Conference Date 2006/5/18(1days)
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Paper Information
Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A 80/100MS/s 76.3/70.1-dB SNDR △Σ ADC for Digital TV Receivers
Sub Title (in English)
Keyword(1) △Σ ADC
Keyword(2) △Σ modulator
Keyword(3) ISDB-T
Keyword(4) DVB-T
Keyword(5) digital TV
Keyword(6) double sampling
1st Author's Name Yoshihisa FUJIMOTO
1st Author's Affiliation Electronic Components and Devices Development Group, Sharp Corporation()
2nd Author's Name Yusuke KANAZAWA
2nd Author's Affiliation Electronic Components and Devices Development Group, Sharp Corporation
3rd Author's Name Pascal LORE
3rd Author's Affiliation Electronic Components and Devices Development Group, Sharp Corporation
4th Author's Name Masayuki MIYAMOTO
4th Author's Affiliation Electronic Components Group, Sharp Corporation
Date 2006-05-26
Paper # ICD2006-31
Volume (vol) vol.106
Number (no) 71
Page pp.pp.-
#Pages 6
Date of Issue