Presentation 2006-04-14
A 16M bit SRAM with improved characteristics using DRAM technology
Yuji KIHARA, Yasushi NAKASHIMA, Takashi IZUTSU, Masayuki NAKAMOTO, Tsutomu YOSHIHARA,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) A 16Mbit Low power SRAM with 0.98um^2 cells using 0.15um DRAM and TFT technology has been developed. A new type memory cell technology achieves enough low power, low cost and high soft error immunity with out large investment. By these improved characteristics some customers at industrial machines and handy devices decided to use this new type of SRAM by compatibility with SRAM.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) SRAM / SuperSRAM / Soft error free / small size SRAM memory cell
Paper # ICD2006-15
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Committee ICD
Conference Date 2006/4/6(1days)
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Paper Information
Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A 16M bit SRAM with improved characteristics using DRAM technology
Sub Title (in English)
Keyword(1) SRAM
Keyword(2) SuperSRAM
Keyword(3) Soft error free
Keyword(4) small size SRAM memory cell
1st Author's Name Yuji KIHARA
1st Author's Affiliation Renesas Technology Corporation()
2nd Author's Name Yasushi NAKASHIMA
2nd Author's Affiliation Renesas Technology Corporation
3rd Author's Name Takashi IZUTSU
3rd Author's Affiliation Renesas Technology Corporation
4th Author's Name Masayuki NAKAMOTO
4th Author's Affiliation Renesas Technology Corporation
5th Author's Name Tsutomu YOSHIHARA
5th Author's Affiliation Waseda University Graduated School
Date 2006-04-14
Paper # ICD2006-15
Volume (vol) vol.106
Number (no) 2
Page pp.pp.-
#Pages 4
Date of Issue