Presentation 2006-04-14
High Performance 16Mb MRAM for Portable Applications
Yuui SHIMIZU, Yoshihisa IWATA, Kenji TSUCHIDA, Tsuneo INABA, Ryosuke TAKIZAWA, Yoshihiro UEDA, Kiyotaro ITAGAKI, Yoshiaki ASAO, HOSOTANI Keiji /, Sumio IKEGAWA, Tadashi KAI, Masahiko NAKAYAMA, Hiroaki YODA,
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Abstract(in English) Magnetoresistive random access memory (MRAM) is expected to become a universal memory solution, because of the features of non-volatility, unlimited write cycles and fast random access speed. In this paper, we designed a 16Mb MRAM compatible with asyncronous/synchoronous pseudo SRAMs and fabricated to target a commercial product. Fork wiring scheme is adapted to reduce the parasitic resistance. And the array architecture which separate write bit line and read bit line is purposed to realize the fast read access. Finally, we realized chip size shrink of 32% compared with conventional chip and 100MHz function. And special shape MTJ which reduces write current by 20% is integrated. Moreover, Fork wiring scheme improved half-selected disturbance immunity by 20%. We realized high performance 16Mb MRAM suitable for portable applications.
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Keyword(in English) MRAM / Burst mode / Fork wiring / WBL/RBL separation / Disturb
Paper # ICD2006-13
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Committee ICD
Conference Date 2006/4/6(1days)
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Paper Information
Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) High Performance 16Mb MRAM for Portable Applications
Sub Title (in English)
Keyword(1) MRAM
Keyword(2) Burst mode
Keyword(3) Fork wiring
Keyword(4) WBL/RBL separation
Keyword(5) Disturb
1st Author's Name Yuui SHIMIZU
1st Author's Affiliation SoC Research and Development Center, Toshiba Corporation()
2nd Author's Name Yoshihisa IWATA
2nd Author's Affiliation SoC Research and Development Center, Toshiba Corporation
3rd Author's Name Kenji TSUCHIDA
3rd Author's Affiliation SoC Research and Development Center, Toshiba Corporation
4th Author's Name Tsuneo INABA
4th Author's Affiliation SoC Research and Development Center, Toshiba Corporation
5th Author's Name Ryosuke TAKIZAWA
5th Author's Affiliation SoC Research and Development Center, Toshiba Corporation
6th Author's Name Yoshihiro UEDA
6th Author's Affiliation SoC Research and Development Center, Toshiba Corporation
7th Author's Name Kiyotaro ITAGAKI
7th Author's Affiliation SoC Research and Development Center, Toshiba Corporation
8th Author's Name Yoshiaki ASAO
8th Author's Affiliation SoC Research and Development Center, Toshiba Corporation
9th Author's Name HOSOTANI Keiji /
9th Author's Affiliation / SoC Research and Development Center, Toshiba Corporation
10th Author's Name Sumio IKEGAWA
10th Author's Affiliation Corporate Research and Development Center, Toshiba Corporation
11th Author's Name Tadashi KAI
11th Author's Affiliation Corporate Research and Development Center, Toshiba Corporation
12th Author's Name Masahiko NAKAYAMA
12th Author's Affiliation Corporate Research and Development Center, Toshiba Corporation
13th Author's Name Hiroaki YODA
13th Author's Affiliation SoC Research and Development Center, Toshiba Corporation
Date 2006-04-14
Paper # ICD2006-13
Volume (vol) vol.106
Number (no) 2
Page pp.pp.-
#Pages 5
Date of Issue