| Presentation | 2006-04-13 A 65nm Low-Power Embedded DRAM with Extended Data-Retention Sleep Mode Tomohisa TAKAI, Takeshi NAGAI, Masaharu WADA, Hitoshi IWAI, Mariko KAKU, Atsushi SUZUKI, Naoko ITOGA, Takayuki MIYAZAKI, Hiroyuki TAKENAKA, Takehiko HOJO, Shinji MIYANO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | An Extended Data Retention (EDR) sleep mode with on-chip ECC and the MT-CMOS technique is proposed for the embedded DRAM stand-by power reduction. In the sleep mode, the retention time is 8 times longer by ECC and the leakage current is reduced to less than 13% compared with normal operation mode. Since ECC operates only in the EDR sleep mode, read/write performance is not degraded. A 65nm low power embedded DRAM macro with 400MHz operation and 0.39mW of data retention power is realized. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Embedded DRAM / Low Power / ECC circuit / MT-CMOS technique |
| Paper # | ICD2006-2 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2006/4/6(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 65nm Low-Power Embedded DRAM with Extended Data-Retention Sleep Mode |
| Sub Title (in English) | |
| Keyword(1) | Embedded DRAM |
| Keyword(2) | Low Power |
| Keyword(3) | ECC circuit |
| Keyword(4) | MT-CMOS technique |
| 1st Author's Name | Tomohisa TAKAI |
| 1st Author's Affiliation | Toshiba Corporation Semiconductor Company() |
| 2nd Author's Name | Takeshi NAGAI |
| 2nd Author's Affiliation | Toshiba Corporation Semiconductor Company |
| 3rd Author's Name | Masaharu WADA |
| 3rd Author's Affiliation | Toshiba Corporation Semiconductor Company |
| 4th Author's Name | Hitoshi IWAI |
| 4th Author's Affiliation | Toshiba Corporation Semiconductor Company |
| 5th Author's Name | Mariko KAKU |
| 5th Author's Affiliation | Toshiba Corporation Semiconductor Company |
| 6th Author's Name | Atsushi SUZUKI |
| 6th Author's Affiliation | Toshiba Corporation Semiconductor Company |
| 7th Author's Name | Naoko ITOGA |
| 7th Author's Affiliation | Toshiba Corporation Semiconductor Company |
| 8th Author's Name | Takayuki MIYAZAKI |
| 8th Author's Affiliation | Toshiba Corporation Semiconductor Company |
| 9th Author's Name | Hiroyuki TAKENAKA |
| 9th Author's Affiliation | Toshiba Microelectronics Corporation |
| 10th Author's Name | Takehiko HOJO |
| 10th Author's Affiliation | Toshiba Corporation Semiconductor Company |
| 11th Author's Name | Shinji MIYANO |
| 11th Author's Affiliation | Toshiba Corporation Semiconductor Company |
| Date | 2006-04-13 |
| Paper # | ICD2006-2 |
| Volume (vol) | vol.106 |
| Number (no) | 2 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |