| Presentation | 2006-04-14 Improvement for Execution Stage in Fault-Tolerant Pipeline Processor Yousuke NAKAMURA, Kei HIRAKI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | When a CPU has highly fault tolerance, each component have to have highly fault tolerance. When faults occur in a functional unit that a Pipeline Processor has, program execution speed is decreased. In this paper, by using re-configuration, we decrease ratio of speed degradation, when a permanent fault occur. When a functional unit is divided into fine grain, extra circuit for calculation is required. We evaluate circuit overhead when functional unit is divided. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | pipeline / permanent fault |
| Paper # | CPSY2006-10,DC2006-10 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2006/4/7(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Improvement for Execution Stage in Fault-Tolerant Pipeline Processor |
| Sub Title (in English) | |
| Keyword(1) | pipeline |
| Keyword(2) | permanent fault |
| 1st Author's Name | Yousuke NAKAMURA |
| 1st Author's Affiliation | The University of Tokyo, Graduate School of Information Science and Technology() |
| 2nd Author's Name | Kei HIRAKI |
| 2nd Author's Affiliation | The University of Tokyo, Graduate School of Information Science and Technology |
| Date | 2006-04-14 |
| Paper # | CPSY2006-10,DC2006-10 |
| Volume (vol) | vol.106 |
| Number (no) | 4 |
| Page | pp.pp.- |
| #Pages | 6 |
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