Presentation 2006-04-14
A DFT for PEs of Coarse Grained Dynamically Reconfigurable Devices
Kentaroh KATOH, Yumin YAO, Kazuteru NAMBA, Hideo ITO,
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Abstract(in English) This paper proposes a BIST (Built-In Self Test) method for testing the PEs (Processing Elements) of multi-context based dynamically reconfigurable processor. We use flip-flops existing in PEs to constitute the test circuit which has the function of LFSR (Linear Feedback Shift Register) and MISR (Multiple Input Signature Register) as DFT (Design For Testability). This method can reduce test execution time while maintaining the high rate of fault coverage. Evaluation of the proposed method examined on DRP-1, a coarse-grained Dynamically Reconfiguration Processor developed by NEC electronics in 2002 is presented. The number of test configurations and test execution time can be reduced 59.0% and 89.3% respectively compared to a deterministic test with 4.3% area overhead.
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Keyword(in English) Coarse Grained Dynamically Reconfigurable Devices / DRP / DFT / PE
Paper # CPSY2006-4,DC2006-4
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Committee DC
Conference Date 2006/4/7(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A DFT for PEs of Coarse Grained Dynamically Reconfigurable Devices
Sub Title (in English)
Keyword(1) Coarse Grained Dynamically Reconfigurable Devices
Keyword(2) DRP
Keyword(3) DFT
Keyword(4) PE
1st Author's Name Kentaroh KATOH
1st Author's Affiliation Graduate School of Science and Technology, Chiba University()
2nd Author's Name Yumin YAO
2nd Author's Affiliation Graduate School of Science and Technology, Chiba University
3rd Author's Name Kazuteru NAMBA
3rd Author's Affiliation Department of Information and Image Sciences, Chiba University
4th Author's Name Hideo ITO
4th Author's Affiliation Department of Information and Image Sciences, Chiba University
Date 2006-04-14
Paper # CPSY2006-4,DC2006-4
Volume (vol) vol.106
Number (no) 4
Page pp.pp.-
#Pages 6
Date of Issue