| Presentation | 2006/3/7 Dsign Method of System LSI with Three-Dimensional Transistor (FinFET) : Reduction of Pattern Area Sigeyoshi Watanabe, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | New design method of system LSI with FinFET has been developed. Using planar+FinFET architecture the pattern area of system LSI designed by cell library can be reduced to about 30% compared with the conventional planar case. New design method is a promising candidate for realizing future high performance, high-density system LSI. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | system LSI / FinFET / channel width / sidewall channel width / cell library / TIS |
| Paper # | SDM2005-266 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 2006/3/7(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Dsign Method of System LSI with Three-Dimensional Transistor (FinFET) : Reduction of Pattern Area |
| Sub Title (in English) | |
| Keyword(1) | system LSI |
| Keyword(2) | FinFET |
| Keyword(3) | channel width |
| Keyword(4) | sidewall channel width |
| Keyword(5) | cell library |
| Keyword(6) | TIS |
| 1st Author's Name | Sigeyoshi Watanabe |
| 1st Author's Affiliation | Department of Information Science, Shonan Institute of Technology() |
| Date | 2006/3/7 |
| Paper # | SDM2005-266 |
| Volume (vol) | vol.105 |
| Number (no) | 654 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |