| Presentation | 2006/3/7 Low Power Design of System LSI in the Presence of Leakage Current of MOSFET Sigeyoshi Watanabe, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Low power design of system LSI in the presence of leakage current has been described. By using parallel processing architecture the active power of embedded processor can be reduced to 1/2 for 2 parallel, 1/5 for 3 parallel case. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | system LSI / parallel processing / MOSFET / leakage current / gate leakage current / sub-threshold leakage current |
| Paper # | SDM2005-265 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 2006/3/7(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Low Power Design of System LSI in the Presence of Leakage Current of MOSFET |
| Sub Title (in English) | |
| Keyword(1) | system LSI |
| Keyword(2) | parallel processing |
| Keyword(3) | MOSFET |
| Keyword(4) | leakage current |
| Keyword(5) | gate leakage current |
| Keyword(6) | sub-threshold leakage current |
| 1st Author's Name | Sigeyoshi Watanabe |
| 1st Author's Affiliation | Department of Information Science, Shonan Institute of Technology() |
| Date | 2006/3/7 |
| Paper # | SDM2005-265 |
| Volume (vol) | vol.105 |
| Number (no) | 654 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |