Presentation 2006-03-03
Interference between PA and VCO in Si System Chip
Koji TSUTSUMI, Shintaro SHINJO, Kazutomi MORI, Noriharu SUEMATSU,
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Abstract(in English) This paper presents analysis of amplitude modulation interference between PA and VCO in Si System Chip. Modeling of the interference path between PA and VCO is performed using the measured result of Si Chip including PA and VCO. Relation of output spectrum degradation to output power is derived from this model, and compared with measured results. Furthermore, to improve the isolation between the PA and the VCO, the back-polish technique of the silicon substrate is proposed. Electro-magnetic simulation and measurement show that this technique is effective to improve the isolation.
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Keyword(in English) SiGe BiCMOS / MMIC / VCO / PA / isolation
Paper # MW2005-182
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Committee MW
Conference Date 2006/2/24(1days)
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Registration To Microwaves (MW)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Interference between PA and VCO in Si System Chip
Sub Title (in English)
Keyword(1) SiGe BiCMOS
Keyword(2) MMIC
Keyword(3) VCO
Keyword(4) PA
Keyword(5) isolation
1st Author's Name Koji TSUTSUMI
1st Author's Affiliation Information Technology R&D Center, Mitsubishi Electric Corporation()
2nd Author's Name Shintaro SHINJO
2nd Author's Affiliation Information Technology R&D Center, Mitsubishi Electric Corporation
3rd Author's Name Kazutomi MORI
3rd Author's Affiliation Information Technology R&D Center, Mitsubishi Electric Corporation
4th Author's Name Noriharu SUEMATSU
4th Author's Affiliation Information Technology R&D Center, Mitsubishi Electric Corporation
Date 2006-03-03
Paper # MW2005-182
Volume (vol) vol.105
Number (no) 626
Page pp.pp.-
#Pages 5
Date of Issue