Presentation 2006-03-03
Software implementation of digital terrestrial television broadcasting 1 segment receiver
Hiroyuki Oyagi, Minoru Okada, Heiichi Yamamoto,
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Abstract(in English) Reconfigurable processor, which is easy to program, as conventional MPU as well, has been release and it achieves the high computational. It makes the development of SDR (Software Defined Radio) easy and cost effectively. This paper shows a design and development of ISDB-T (Integrated Services Digital Broadcasting-Terrestrial) "One-Segment" narrow-band receiver. Reconfigurable processor is configured by the plural processors but differs from stream processing processor and block processing processor. Furthermore, it is necessary to develop effectively the parallel processing by using parallel on plural computing unit, follow the restricted computing unit, memory allocation, bit-width and the number of cycle budget, computation sequence. This paper designs the signal processing flow of the terrestrial digital broadcast 1 segment receiver which uses reconfigurable processor and developing it on the receiver.
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Keyword(in English) digital terrestrial television broadcasting / reconfigurable processor / signal processing / software defined radio
Paper # MoMuC2005-90
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Conference Information
Committee MoMuC
Conference Date 2006/2/23(1days)
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Registration To Mobile Multimedia Communications(MoMuC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Software implementation of digital terrestrial television broadcasting 1 segment receiver
Sub Title (in English)
Keyword(1) digital terrestrial television broadcasting
Keyword(2) reconfigurable processor
Keyword(3) signal processing
Keyword(4) software defined radio
1st Author's Name Hiroyuki Oyagi
1st Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology()
2nd Author's Name Minoru Okada
2nd Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology
3rd Author's Name Heiichi Yamamoto
3rd Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology
Date 2006-03-03
Paper # MoMuC2005-90
Volume (vol) vol.105
Number (no) 624
Page pp.pp.-
#Pages 6
Date of Issue