Presentation 2006/3/10
A minimum cluster depth packing algorithm for LUT-based FPGA
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Abstract(in English) When the circuit is implemented on FPGA, the circuit is covered with LUT (Look-Up Table) and pack their LUTs into a logical blocks called cluster. The process is called packing. When thinking about the wiring delay between clusters, it is difficult to estimate an actual delay strictly if placement and routing of the circuit has not been done yet. Then, the delay model by whom the wiring delay between each cluster is assumed to be constant is used in packing. In this case, the delay of the circuit is decided depending on a cluster depth. In this paper, it proposes a minimum cluster depth packing algorithm for FPGA. The proposal algorithm refers an existing mapping algorithm that minimizes a LUT depth and it makes the circuit which the cluster depth is minimized through two processes "labelling" and "packing". In the comparison experiment with an existing algorithm that used the benchmark circuit, it was confirmed that a cluster depth had been reduced about 30% by the average.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) FPGA / EDA / Packing / Delay reduction
Paper # CPSY2005-84,DC2005-104
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Conference Information
Committee DC
Conference Date 2006/3/10(1days)
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Paper Information
Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A minimum cluster depth packing algorithm for LUT-based FPGA
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) EDA
Keyword(3) Packing
Keyword(4) Delay reduction
1st Author's Name Yuji KATSUKI
1st Author's Affiliation Graduate School of Infomation Science and Electrical Engineering, Kyushu University()
2nd Author's Name Yusuke MATSUNAGA
2nd Author's Affiliation Faculty of Infomation Science and Electrical Engineering, Kyushu University
Date 2006/3/10
Paper # CPSY2005-84,DC2005-104
Volume (vol) vol.105
Number (no) 672
Page pp.pp.-
#Pages 6
Date of Issue