Presentation | 2006/3/9 Instruction Set Evaluation with Register Constraint for Application Specific Processor Design Masayuki MASUDA, Kazuhit ITO, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | The selection of instruction set of a processor greatly influences the processor hardware and execution of software in speed, area, and power. Evaluation of instruction set is an important task in designing a processor specific to a given application. In this paper, a technique to rapidly and precisely evaluate instruction sets for the given application is proposed with consideration of memory access by register constraint. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Application-specific processor / Processor design / Instruction-set evaluation / DAG covering / Branch and bound |
Paper # | DC2005-85 |
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Conference Information | |
Committee | DC |
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Conference Date | 2006/3/9(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Dependable Computing (DC) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Instruction Set Evaluation with Register Constraint for Application Specific Processor Design |
Sub Title (in English) | |
Keyword(1) | Application-specific processor |
Keyword(2) | Processor design |
Keyword(3) | Instruction-set evaluation |
Keyword(4) | DAG covering |
Keyword(5) | Branch and bound |
1st Author's Name | Masayuki MASUDA |
1st Author's Affiliation | Department of Electrical and Electronic Systems, Saitama University() |
2nd Author's Name | Kazuhit ITO |
2nd Author's Affiliation | Department of Electrical and Electronic Systems, Saitama University |
Date | 2006/3/9 |
Paper # | DC2005-85 |
Volume (vol) | vol.105 |
Number (no) | 671 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |