Presentation 2006/3/9
Evaluation of Embedded Chip Multi-Processors using Parallelized MiBench Suits
Yasuki TANABE, Masato SUMIYOSI, Hideharu AMANO,
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Abstract(in English) Today, even embedded systems are required to process complicated programs with large size data considering both performance and energy consumption. Chip multi-processors (CMPs) have received an attention as one of the most promising candidates. Since a lot of applications used in embedded systems have a large degree of data parallelism, CMPs have a potential to enhance the performance by executing these applications in parallel. In this paper we parallelized three applications from MiBench embedded system benchmark suits using data parallelism extracted from the applications and executed these parallelized applications on a simulator that modeled CMPs. And we demonstrate that CMPs can achieve a good execution performance for the applications used in an embedded system.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Embedded Systems / Chip Multi-Processors / Benchmark / Cache Cosistency
Paper # DC2005-84
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Conference Date 2006/3/9(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Evaluation of Embedded Chip Multi-Processors using Parallelized MiBench Suits
Sub Title (in English)
Keyword(1) Embedded Systems
Keyword(2) Chip Multi-Processors
Keyword(3) Benchmark
Keyword(4) Cache Cosistency
1st Author's Name Yasuki TANABE
1st Author's Affiliation Graduate School of Science and Technology, Keio University()
2nd Author's Name Masato SUMIYOSI
2nd Author's Affiliation Graduate School of Science and Technology, Keio University
3rd Author's Name Hideharu AMANO
3rd Author's Affiliation Graduate School of Science and Technology, Keio University
Date 2006/3/9
Paper # DC2005-84
Volume (vol) vol.105
Number (no) 671
Page pp.pp.-
#Pages 6
Date of Issue