Presentation	2006-03-16 Hardware Implementation and Tamper Resistance Evaluation of a Hash Function Jun KITAHARA, Katsuyuki OKEYA,
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Abstract(in English)	The hash function SHA-1 was implemented on FPGA (Field Programmable Gate Array). The measurement environment of the consumption electric power of FPGA was made for evaluation of tamper resistance. We presumed side channel attack by the consumption electric power. SHA-1 was implemented in this measurement environment, and the consumption electric power during the operation was observed. It could guess the operation of 80 rounds. Characteristics with relation to input were found in a certain round.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Hash function / Hardware / Tamper resistance / Side channel attack
Paper #	IT2005-80,ISEC2005-137,WBS2005-94
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Conference Information
Committee	ISEC
Conference Date	2006/3/9(1days)
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Paper Information
Registration To	Information Security (ISEC)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Hardware Implementation and Tamper Resistance Evaluation of a Hash Function
Sub Title (in English)
Keyword(1)	Hash function
Keyword(2)	Hardware
Keyword(3)	Tamper resistance
Keyword(4)	Side channel attack
1st Author's Name	Jun KITAHARA
1st Author's Affiliation	()
2nd Author's Name	Katsuyuki OKEYA
2nd Author's Affiliation
Date	2006-03-16
Paper #	IT2005-80,ISEC2005-137,WBS2005-94
Volume (vol)	vol.105
Number (no)	663
Page	pp.pp.-
#Pages	4
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