| Presentation | 2006-03-16 Degradation of Tamper Resistant LSI by Parameter Variation of Scaled Devices and its Countermeasures Hiroshi YAMAUCHI, Makoto IKEDA, Kunihiro ASADA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Constant-characteristic power dissipation LSI architecture is proposed as countermeasure of power analysis and electromagnetic analysis. We proposed that variation of threshold voltage can become new side-channel in this tamper-resistant LSI architecture. Based on this proposal, we proposed electromagnetic analysis to tamper-resistant LSI using elemental variation. Proposal analysis simulation to tamper-resistant LSI was actually performed and its validity was confirmed. Furthermore, we proposed countermeasures of proposal analysis and examined prospect of vulnerability in further scaled process. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | elemental variation / tamper resistant LSI / electromagnetic analysis / power analysis / side-channel / DES |
| Paper # | IT2005-79,ISEC2005-136,WBS2005-93 |
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| Conference Information | |
| Committee | ISEC |
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| Conference Date | 2006/3/9(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Information Security (ISEC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Degradation of Tamper Resistant LSI by Parameter Variation of Scaled Devices and its Countermeasures |
| Sub Title (in English) | |
| Keyword(1) | elemental variation |
| Keyword(2) | tamper resistant LSI |
| Keyword(3) | electromagnetic analysis |
| Keyword(4) | power analysis |
| Keyword(5) | side-channel |
| Keyword(6) | DES |
| 1st Author's Name | Hiroshi YAMAUCHI |
| 1st Author's Affiliation | Faculty of Engineering, University of Tokyo() |
| 2nd Author's Name | Makoto IKEDA |
| 2nd Author's Affiliation | VLSI Design and Education Center, University of Tokyo |
| 3rd Author's Name | Kunihiro ASADA |
| 3rd Author's Affiliation | VLSI Design and Education Center, University of Tokyo |
| Date | 2006-03-16 |
| Paper # | IT2005-79,ISEC2005-136,WBS2005-93 |
| Volume (vol) | vol.105 |
| Number (no) | 663 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |