| Presentation | 2006-03-16 Experimental Results on INSTAC-8 Compliant Board Yukiyasu TSUNOO, Toru HISAKADO, Etsuko TSUJIHARA, Tsutomu MATSUMOTO, Shinichi KAWAMURA, Kouichi FUJISAKI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents the results of three kinds of Side-channel attacks, experimentally made against software-implemented ciphers on INSTAC-8 Compliant Board. Three side-channel attacks referred above are Differential Power Analysis, Electro Magnetic Analysis, and Simple Power Analysis. The first experiment, where DPA was applied on DBS cipher, was conducted by the designers of INSTAC-8, in order to check the board if it works as intended. The second experiment, where EMA was made on mini-cipher, that is, a lookup of substitution box after key addition, was carried out and was reported in TECHNICAL REPORT OF IEICE by Takahashi et al. The third one, where SPA was made against A5/1 cipher, was performed by Tsunoo et al. in May 2005. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | INSTAC-8 / Side-channel attack / SPA / DPA / EMA |
| Paper # | IT2005-78,ISEC2005-135,WBS2005-92 |
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| Conference Information | |
| Committee | ISEC |
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| Conference Date | 2006/3/9(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Information Security (ISEC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Experimental Results on INSTAC-8 Compliant Board |
| Sub Title (in English) | |
| Keyword(1) | INSTAC-8 |
| Keyword(2) | Side-channel attack |
| Keyword(3) | SPA |
| Keyword(4) | DPA |
| Keyword(5) | EMA |
| 1st Author's Name | Yukiyasu TSUNOO |
| 1st Author's Affiliation | TSRC: Tamper-resistance Standardization Research Committee, INSTAC: Information Technology Research and Standardization Center, JSA: Japanese Standardization Association:NEC Corporation() |
| 2nd Author's Name | Toru HISAKADO |
| 2nd Author's Affiliation | NEC Corporation |
| 3rd Author's Name | Etsuko TSUJIHARA |
| 3rd Author's Affiliation | Y. D. K. Co., Ltd. |
| 4th Author's Name | Tsutomu MATSUMOTO |
| 4th Author's Affiliation | TSRC: Tamper-resistance Standardization Research Committee, INSTAC: Information Technology Research and Standardization Center, JSA: Japanese Standardization Association:Yokohama National University, Graduate School of Environment and Information Sciences |
| 5th Author's Name | Shinichi KAWAMURA |
| 5th Author's Affiliation | TSRC: Tamper-resistance Standardization Research Committee, INSTAC: Information Technology Research and Standardization Center, JSA: Japanese Standardization Association:Corporate Research & Development Center, Toshiba Corporation |
| 6th Author's Name | Kouichi FUJISAKI |
| 6th Author's Affiliation | TSRC: Tamper-resistance Standardization Research Committee, INSTAC: Information Technology Research and Standardization Center, JSA: Japanese Standardization Association:Corporate Research & Development Center, Toshiba Corporation |
| Date | 2006-03-16 |
| Paper # | IT2005-78,ISEC2005-135,WBS2005-92 |
| Volume (vol) | vol.105 |
| Number (no) | 663 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |