Presentation 2006-03-10
A reconfigurable circuit to utilize and compensate device variations
Manabu KOTANI, Kazuya KATSUKI, Kosuke OGATA, Kazutoshi KOBAYASHI, Hidetoshi ONODERA,
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Abstract(in English) This paper provides the principle and architecture of a reconfigurable circuit utilizing Within-Die variaitions and shows a experimental results of speed and yield enhancement. We designed and fabricated a FPGA with a functionality to measure variations with 2% of high accuracy. The overhead caused by the mechanism is regarded as sufficient small. A verification with a simple model circuit shows that performance of the circuit is enhanced by 4% in average, which is the same amount as the width of variations. The yield is enhanced 32% to the worst case.
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Keyword(in English) variations / reconfigure / FPGA / DFM
Paper # VLD2005-130,ICD2005-247
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Conference Date 2006/3/3(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A reconfigurable circuit to utilize and compensate device variations
Sub Title (in English)
Keyword(1) variations
Keyword(2) reconfigure
Keyword(3) FPGA
Keyword(4) DFM
1st Author's Name Manabu KOTANI
1st Author's Affiliation Graduate School of Informatics, Kyoto University()
2nd Author's Name Kazuya KATSUKI
2nd Author's Affiliation Graduate School of Informatics, Kyoto University
3rd Author's Name Kosuke OGATA
3rd Author's Affiliation Graduate School of Informatics, Kyoto University
4th Author's Name Kazutoshi KOBAYASHI
4th Author's Affiliation Graduate School of Informatics, Kyoto University
5th Author's Name Hidetoshi ONODERA
5th Author's Affiliation Graduate School of Informatics, Kyoto University
Date 2006-03-10
Paper # VLD2005-130,ICD2005-247
Volume (vol) vol.105
Number (no) 647
Page pp.pp.-
#Pages 6
Date of Issue