| Presentation | 2006-03-10 Coarse-grained Reconfigurable Hardware with Mapping Mechanisms of Floating Point Operations and Chained Additions Hidemi AKUTSU, Shinji KIMURA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, researches on coarse-grained reconfigurable hardware are studied hard, since such architecture needs less information at the configuration and is suitable for dynamic reconfiguration. Coarse-grained reconfigurable architecture also has a chance to implement the same functionality with small area, small delay time and low power compared to fine-grained reconfigurable hardware such as FPGA. Current coarse-grained hardware do not care about the chaining of additions/subtractions for consecutive additions/subtractions, which is effective to the fast execution of consecutive aditions/subtractions. They also do not care about the floating-point operations which might be major in the emulation of software algorithms. In the paper, we propose a new reconfigurable hardware architecture considering the mapping of the chaining of additions/subtractions and that of floating point operations. We also shows an LSI implementation of such architecture. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Coarse-grained / ALU array / Reconfigurable Hardware / Floating point operations / Chaining of additions |
| Paper # | VLD2005-129,ICD2005-246 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2006/3/3(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Coarse-grained Reconfigurable Hardware with Mapping Mechanisms of Floating Point Operations and Chained Additions |
| Sub Title (in English) | |
| Keyword(1) | Coarse-grained |
| Keyword(2) | ALU array |
| Keyword(3) | Reconfigurable Hardware |
| Keyword(4) | Floating point operations |
| Keyword(5) | Chaining of additions |
| 1st Author's Name | Hidemi AKUTSU |
| 1st Author's Affiliation | Graduate School of Information, Production and System, Waseda University() |
| 2nd Author's Name | Shinji KIMURA |
| 2nd Author's Affiliation | Graduate School of Information, Production and System, Waseda University |
| Date | 2006-03-10 |
| Paper # | VLD2005-129,ICD2005-246 |
| Volume (vol) | vol.105 |
| Number (no) | 647 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |