| Presentation | 2006-03-09 Conversion Method from High-level Hardware Description to Equivalence Logic Formulae Kwanghoon JUNG, Shinji KIMURA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | With the enlargement of the integration size on one LSI chip, high-level design methods using C-language are applied to the design of LSI chips, and the requirement for high-level verification methods becomes large. At the high-level, the simulation speed is known to be high, but it is hard to verify the functionality with only the simulation, and formal methods are suitable especially for the comparison of the original and optimized circuits. In the paper, we focus on the equivalence checking methods based on equivalence logic such as CVC (Cooperating Validity Checker), and show a verification method of C/Verilog descriptions by generating CVC formulae from C/Verilog sources. Since the verification time using CVC is influenced by the size of formulae, we should devise conversion methods from C/Verilog sources. We introduce several conversion methods and show their effectiveness. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | formal verification / high-level functional verification / Verilog/C equivalence checking / CVC (Cooperating Validity Checker) |
| Paper # | VLD2005-121,ICD2005-238 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2006/3/2(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Conversion Method from High-level Hardware Description to Equivalence Logic Formulae |
| Sub Title (in English) | |
| Keyword(1) | formal verification |
| Keyword(2) | high-level functional verification |
| Keyword(3) | Verilog/C equivalence checking |
| Keyword(4) | CVC (Cooperating Validity Checker) |
| 1st Author's Name | Kwanghoon JUNG |
| 1st Author's Affiliation | Graduate School of Information, Production and Systems, Waseda University /() |
| 2nd Author's Name | Shinji KIMURA |
| 2nd Author's Affiliation | |
| Date | 2006-03-09 |
| Paper # | VLD2005-121,ICD2005-238 |
| Volume (vol) | vol.105 |
| Number (no) | 646 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |