| Presentation | 2006-03-09 A pipeline architecture optimization algorithm for SIMD-type processor core synthesis Akira KURIHARA, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes an algorithm to optimize the pipeline architecture of processor core to be synthesized. The algorithm can be integrated into the synthesis system for an application-specific SIMD processor core. A SIMD processor core has SIMD functional units whose critical path delay is relatively large and it usually determines operating frequency. By applying pipelining technique to the processor core, its operating frequency can be increased without adding too much area. However, increasing the number of pipeline stages does not always lead to reduction in execution time because of hazards, thus the optimum pipeline architecture should be searched during the processor core synthesis. In the algorithm, first a set of pipeline architectures with different number of pipeline stages is defined. Next, for each defined pipeline architecture, the number of hardware units which are added to the processor core is optimized to satisfy the given timing constraint. Last, the pipeline architecture with the smallest area among the defined pipeline architectures is selected as an optimum solution. We also show the promising experimental results on the algorithm evaluation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | pipeline architecture optimization / hardware/software cosynthesis / processor core synthesis / pipelined functional unit |
| Paper # | VLD2005-115,ICD2005-232 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2006/3/2(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A pipeline architecture optimization algorithm for SIMD-type processor core synthesis |
| Sub Title (in English) | |
| Keyword(1) | pipeline architecture optimization |
| Keyword(2) | hardware/software cosynthesis |
| Keyword(3) | processor core synthesis |
| Keyword(4) | pipelined functional unit |
| 1st Author's Name | Akira KURIHARA |
| 1st Author's Affiliation | Dept. of Computer Science, Waseda University() |
| 2nd Author's Name | Nozomu TOGAWA |
| 2nd Author's Affiliation | Dept. of Computer Science, Waseda University |
| 3rd Author's Name | Masao YANAGISAWA |
| 3rd Author's Affiliation | Dept. of Computer Science, Waseda University |
| 4th Author's Name | Tatsuo OHTSUKI |
| 4th Author's Affiliation | Dept. of Computer Science, Waseda University |
| Date | 2006-03-09 |
| Paper # | VLD2005-115,ICD2005-232 |
| Volume (vol) | vol.105 |
| Number (no) | 646 |
| Page | pp.pp.- |
| #Pages | 6 |
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