Presentation 2006-03-09
A Code Placement Technique for Power Minimization of Way-Predicting Caches
Yohei IMAI, Shinya HONDA, Hiroyuki TOMIYAMA, Hiroaki TAKADA,
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Abstract(in English) Recently, the ratio of power consumption by caches on a processor tends to increase. We propose an improved code placement technique for way-prediction caches in order to reduce the cache energy. The energy of way-prediction cache depends on way-prediction miss rate. Way-prediction misses are caused by a similar reason to cache misses. The proposed code replacement technique reduces both cache miss rate and way-prediction miss rate. As a result, energy consumption of caches can be reduced effectively. Our experiments confirm that the proposed code placement technique reduces cache energy more effectively than traditional techniques.
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Keyword(in English) low power / caches / way prediction / code placement technique
Paper # VLD2005-114,ICD2005-231
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Conference Date 2006/3/2(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Code Placement Technique for Power Minimization of Way-Predicting Caches
Sub Title (in English)
Keyword(1) low power
Keyword(2) caches
Keyword(3) way prediction
Keyword(4) code placement technique
1st Author's Name Yohei IMAI
1st Author's Affiliation Graduate School of Information Science, Nagoya University()
2nd Author's Name Shinya HONDA
2nd Author's Affiliation Information Technology Center, Nagoya University
3rd Author's Name Hiroyuki TOMIYAMA
3rd Author's Affiliation Graduate School of Information Science, Nagoya University
4th Author's Name Hiroaki TAKADA
4th Author's Affiliation Graduate School of Information Science, Nagoya University
Date 2006-03-09
Paper # VLD2005-114,ICD2005-231
Volume (vol) vol.105
Number (no) 646
Page pp.pp.-
#Pages 6
Date of Issue