| Presentation | 2006/2/10 Speed-up method of delay sensitized path calculation in transition delay test Shyuji HAMADA, Toshiyuki MAEDA, Atsuo TAKATORI, Yasuyuki NOZDUYAMA, Yasuo SATO, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The progress of fabrication process and design technology lead to the increase of small delay failures in SoC. To achieve an accurate evaluation of delay testing quality, the authors proposed a statistical approach that calculates actual sensitized path lengths that detect small delay defects. However, the calculation requires a huge amount of CPU time. Therefore, a fast method was strongly needed. The paper addresses the efficient method to calculate sensitized path lengths and shows its experimental results regarding to CPU time and accuracy. Our experiments show that the method achieves the calculation with high speed and high accuracy. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Transition delay test / Statistical Delay Quality Model / Path length |
| Paper # | DC2005-83 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2006/2/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Speed-up method of delay sensitized path calculation in transition delay test |
| Sub Title (in English) | |
| Keyword(1) | Transition delay test |
| Keyword(2) | Statistical Delay Quality Model |
| Keyword(3) | Path length |
| 1st Author's Name | Shyuji HAMADA |
| 1st Author's Affiliation | Semiconductor Technology Academic Research Center() |
| 2nd Author's Name | Toshiyuki MAEDA |
| 2nd Author's Affiliation | Semiconductor Technology Academic Research Center |
| 3rd Author's Name | Atsuo TAKATORI |
| 3rd Author's Affiliation | Semiconductor Technology Academic Research Center |
| 4th Author's Name | Yasuyuki NOZDUYAMA |
| 4th Author's Affiliation | Semiconductor Technology Academic Research Center |
| 5th Author's Name | Yasuo SATO |
| 5th Author's Affiliation | Semiconductor Technology Academic Research Center |
| Date | 2006/2/10 |
| Paper # | DC2005-83 |
| Volume (vol) | vol.105 |
| Number (no) | 607 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |