Presentation 2006/2/10
On generation of transition faults test patterns in consideration of the path length in broadside testing
Shohei MORISHIMA, Akane TAKUMA, Seiji KAJIHARA, Xiaoqing WEN, Toshiyuki MAEDA, Shuji HAMADA, Yasuo SATO,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) Shrinking of manufacturing process and improvement in the speed of LSI circuits, and the yield loss by the defects which cause an error with the increase of small delay has been a problem. In this paper, we propose a test generation method that defects transition faults due to the small delay. The proposed method generates test patterns so that the path with the signal transition through a fault site becomes as long as possible. The feature of the proposed method is that we prepare two ATPG algorithms, which are activation-oriented and propagation-oriented, and decide which algorithm should be applied for each fault. Experimental results, in which test patterns generated are evaluated, shows the effectiveness of the proposed method.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Test pattern generation / Scan design / Transition fault
Paper # DC2005-81
Date of Issue

Conference Information
Committee DC
Conference Date 2006/2/10(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) On generation of transition faults test patterns in consideration of the path length in broadside testing
Sub Title (in English)
Keyword(1) Test pattern generation
Keyword(2) Scan design
Keyword(3) Transition fault
1st Author's Name Shohei MORISHIMA
1st Author's Affiliation Kyushu Institute of Technology()
2nd Author's Name Akane TAKUMA
2nd Author's Affiliation Kyushu Institute of Technology
3rd Author's Name Seiji KAJIHARA
3rd Author's Affiliation Kyushu Institute of Technology
4th Author's Name Xiaoqing WEN
4th Author's Affiliation Kyushu Institute of Technology
5th Author's Name Toshiyuki MAEDA
5th Author's Affiliation Semiconductor Technology Academic Research Center
6th Author's Name Shuji HAMADA
6th Author's Affiliation Semiconductor Technology Academic Research Center
7th Author's Name Yasuo SATO
7th Author's Affiliation Semiconductor Technology Academic Research Center
Date 2006/2/10
Paper # DC2005-81
Volume (vol) vol.105
Number (no) 607
Page pp.pp.-
#Pages 6
Date of Issue