Presentation 2006/2/10
A New Class of Sequential Circuits with Acyclic Test Generation Complexity
Chia Yee Ooi,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) This paper introduces a new class of sequential circuits called acyclically testable sequential circuits, whose test generation complexity is equivalent to that of the acyclic sequential circuits. A procedure to perform test generation on acyclically testable sequential circuits is elaborated and a design-for-test (DFT) method to augment an arbitrary sequential circuit into an acyclically testable sequential circuits is also presented. Since the class of acyclically testable sequential circuits is larger than the class of acyclic sequential circuits, the DFT method results in lower area overhead than the partial scan method and still achieves complete fault efficiency. Besides, we show through experiment that the proposed method contributes to lower test application time compared to partial scan method. Moreover, the proposed method allows at-speed testing while the partial scan method does not.
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Keyword(in English) Acyclic testability / test generation complexity / design-for-test
Paper # DC2005-80
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Conference Date 2006/2/10(1days)
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Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A New Class of Sequential Circuits with Acyclic Test Generation Complexity
Sub Title (in English)
Keyword(1) Acyclic testability
Keyword(2) test generation complexity
Keyword(3) design-for-test
1st Author's Name Chia Yee Ooi
1st Author's Affiliation Nara Institute of Science and Technology()
Date 2006/2/10
Paper # DC2005-80
Volume (vol) vol.105
Number (no) 607
Page pp.pp.-
#Pages 6
Date of Issue