Presentation 2006/2/10
A High-Level Memory Test Description Language for Dynamic Reconfigurable Memory Tester and Convertion to VHDL
Satoru MORIYA, Takeshi YANASE, Yukihiro IGUCHI, Shuichi KAMEYAMA, Hiromi SHIMADA,
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Abstract(in English) MM5 developed by Fujitsu is the dynamic reconfigurable memory tester with the high-level test synthesis function. Users can specify test patterns by combining embedded test patterns, and adjusting parameters. However, when they need new test patterns, they have to specify corresponding test pattern generators in VHDL. We proposed a method in which users can specify test patterns using a high-level test pattern description language, and convert them to VHDL. This paper shows a converter which can handle two kinds of memory modules, SDRAMs and DDR SDRAMs. We have described major test patterns using proposed language, and converted to VHDL. We have implemented them on a XILINX FPGA Vertex-II in MM5 using Exempler Logic Leonardo Spectrum ver. 2002b.21, XILINX Project Navigator ver. 6.203i. They can work 119-127 MHz for SDRAM testings, and 75-87 MHz for DDR SDRAM testings on MM5.
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Paper # DC2005-79
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Conference Date 2006/2/10(1days)
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Language JPN
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Title (in English) A High-Level Memory Test Description Language for Dynamic Reconfigurable Memory Tester and Convertion to VHDL
Sub Title (in English)
Keyword(1)
1st Author's Name Satoru MORIYA
1st Author's Affiliation Depertment of Computer Science, Meiji University()
2nd Author's Name Takeshi YANASE
2nd Author's Affiliation Fujitsu Limited
3rd Author's Name Yukihiro IGUCHI
3rd Author's Affiliation Depertment of Computer Science, Meiji University
4th Author's Name Shuichi KAMEYAMA
4th Author's Affiliation Fujitsu Limited
5th Author's Name Hiromi SHIMADA
5th Author's Affiliation Fujitsu Limited
Date 2006/2/10
Paper # DC2005-79
Volume (vol) vol.105
Number (no) 607
Page pp.pp.-
#Pages 6
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