| Presentation | 2006/1/30 Chip-level Performance Maximization using ASIS (Application-specific Interconnect Structure) Wiring Design Concept for 45nm node Noriaki Oda, Hironori Imura, Naoyoshi Kawahara, Masayoshi Tagami, Hiroyuki Kunishima, Shuji Sone, Sadayuki Ohnishi, Kenta Yamada, Yumi Kakuhara, Makoto Sekine, Yoshihiro Hayashi, Kazuyoshi Ueno, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A novel interconnect design concept named "ASIS (Application-specific Interconnect Structure)" is presented for 45nm CMOS performance maximization. Basic scheme of ASIS is that corresponding to applications, such as high-performance, low-power or high reliability, interconnect structure as well as metal thickness is individually optimized in order to maximize chip-level performance matched to the application. Our investigation shows that for low power application, the increased resistivity of scaled-down Cu-wire is not a main issue, so that thinner wire is more advantageous. For high-performance application, partially double pitch structure for local and intermediate layers is advantageous. For high-reliability requirement, CuAl-alloy or CoWP cap-metal is quite effective for boosting reliability. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | 45-nm node / CMOS / Interconnect / low-k / Design / Propagation delay time / Repeater / CuAl / alloy / CoWP / cap-metal |
| Paper # | SDM2005-252 |
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| Conference Information | |
| Committee | SDM |
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| Conference Date | 2006/1/30(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Chip-level Performance Maximization using ASIS (Application-specific Interconnect Structure) Wiring Design Concept for 45nm node |
| Sub Title (in English) | |
| Keyword(1) | 45-nm node |
| Keyword(2) | CMOS |
| Keyword(3) | Interconnect |
| Keyword(4) | low-k |
| Keyword(5) | Design |
| Keyword(6) | Propagation delay time |
| Keyword(7) | Repeater |
| Keyword(8) | CuAl |
| Keyword(9) | alloy |
| Keyword(10) | CoWP |
| Keyword(11) | cap-metal |
| 1st Author's Name | Noriaki Oda |
| 1st Author's Affiliation | NEC Electronics Corporation() |
| 2nd Author's Name | Hironori Imura |
| 2nd Author's Affiliation | NEC Electronics Corporation |
| 3rd Author's Name | Naoyoshi Kawahara |
| 3rd Author's Affiliation | NEC Electronics Corporation |
| 4th Author's Name | Masayoshi Tagami |
| 4th Author's Affiliation | NEC Corporation |
| 5th Author's Name | Hiroyuki Kunishima |
| 5th Author's Affiliation | NEC Electronics Corporation |
| 6th Author's Name | Shuji Sone |
| 6th Author's Affiliation | NEC Electronics Corporation |
| 7th Author's Name | Sadayuki Ohnishi |
| 7th Author's Affiliation | NEC Electronics Corporation |
| 8th Author's Name | Kenta Yamada |
| 8th Author's Affiliation | NEC Electronics Corporation |
| 9th Author's Name | Yumi Kakuhara |
| 9th Author's Affiliation | NEC Electronics Corporation |
| 10th Author's Name | Makoto Sekine |
| 10th Author's Affiliation | NEC Electronics Corporation |
| 11th Author's Name | Yoshihiro Hayashi |
| 11th Author's Affiliation | NEC Corporation |
| 12th Author's Name | Kazuyoshi Ueno |
| 12th Author's Affiliation | NEC Electronics Corporation |
| Date | 2006/1/30 |
| Paper # | SDM2005-252 |
| Volume (vol) | vol.105 |
| Number (no) | 598 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |