| Presentation | 2006/1/30 Mechanism of Moisture Uptake Induced Via Failure and its Impact on 45nm Node Interconnect Design T. Fujimaki, K. Higashi, N. Nakamura, N. Matsunaga, K. Yoshida, M. Hatano, M. Hasunuma, J. Wada, T. Nishioka, K. Akiyama, H. Kawashima, Y. Enomoto, T. Hasegawa, K. Honda, M. Iwai, S. Yamada, F. Matsuoka, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Moisture induced via failure (MIVF) is studied for 45nm interconnect technology using porous low-k films. Test patterns are designed to examine the layout dependence of the MIVF. Some fundamental and important layout dependencies of the via resistance increase are investigated for the first time. Local wiring pattern density close to via and dummy wiring pattern area size strongly affect via resistance increase. A model with moisture ventilation can successfully explain those layout dependencies. It is confirmed that the MIVF is completely suppressed by the control of dummy pattern layout. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Porous / Low-k / Moisture uptake / Dummy wiring / Via failure |
| Paper # | SDM2005-251 |
| Date of Issue |
| Conference Information | |
| Committee | SDM |
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| Conference Date | 2006/1/30(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Silicon Device and Materials (SDM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Mechanism of Moisture Uptake Induced Via Failure and its Impact on 45nm Node Interconnect Design |
| Sub Title (in English) | |
| Keyword(1) | Porous |
| Keyword(2) | Low-k |
| Keyword(3) | Moisture uptake |
| Keyword(4) | Dummy wiring |
| Keyword(5) | Via failure |
| 1st Author's Name | T. Fujimaki |
| 1st Author's Affiliation | Semiconductor Company, Toshiba Corporation() |
| 2nd Author's Name | K. Higashi |
| 2nd Author's Affiliation | Semiconductor Company, Toshiba Corporation |
| 3rd Author's Name | N. Nakamura |
| 3rd Author's Affiliation | Semiconductor Company, Toshiba Corporation |
| 4th Author's Name | N. Matsunaga |
| 4th Author's Affiliation | Semiconductor Company, Toshiba Corporation |
| 5th Author's Name | K. Yoshida |
| 5th Author's Affiliation | MOS Logic Device Engineering Department, Toshiba Microelectronics Corporation |
| 6th Author's Name | M. Hatano |
| 6th Author's Affiliation | Semiconductor Company, Toshiba Corporation |
| 7th Author's Name | M. Hasunuma |
| 7th Author's Affiliation | Semiconductor Company, Toshiba Corporation |
| 8th Author's Name | J. Wada |
| 8th Author's Affiliation | Semiconductor Company, Toshiba Corporation |
| 9th Author's Name | T. Nishioka |
| 9th Author's Affiliation | Semiconductor Company, Toshiba Corporation |
| 10th Author's Name | K. Akiyama |
| 10th Author's Affiliation | Semiconductor Company, Toshiba Corporation |
| 11th Author's Name | H. Kawashima |
| 11th Author's Affiliation | Semiconductor Business Unit, Sony Corporation |
| 12th Author's Name | Y. Enomoto |
| 12th Author's Affiliation | Semiconductor Business Unit, Sony Corporation |
| 13th Author's Name | T. Hasegawa |
| 13th Author's Affiliation | Semiconductor Business Unit, Sony Corporation |
| 14th Author's Name | K. Honda |
| 14th Author's Affiliation | Semiconductor Company, Toshiba Corporation |
| 15th Author's Name | M. Iwai |
| 15th Author's Affiliation | Semiconductor Company, Toshiba Corporation |
| 16th Author's Name | S. Yamada |
| 16th Author's Affiliation | Semiconductor Company, Toshiba Corporation |
| 17th Author's Name | F. Matsuoka |
| 17th Author's Affiliation | Semiconductor Company, Toshiba Corporation |
| Date | 2006/1/30 |
| Paper # | SDM2005-251 |
| Volume (vol) | vol.105 |
| Number (no) | 598 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |