Presentation 2006-02-17
Development of Test Circuit for Spotty Byte Error Control Codes
Takeshi SASADA, Haruhiko KANEKO, Hideki IMASHIRO,
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Abstract(in English) Error control coding is essential for semiconductor memory systems used in the space radiation environment because single event upsets (SEUs) are often observed in these memory systems. Conventional error control codes, such as Hamming codes and Reed-Solomon (RS) codes, are not necessarily suitable for the memory systems, because Hamming codes cannot correct random multiple-bit errors while RS codes require a large number of check bits for large byte length b. Recently, a new class of error control codes suitable for correcting multiple bit errors in a byte, called spotty byte error control codes, has been proposed. This report presents development of encoder and parallel decoder for three classes of RS codes and for three classes of spotty byte error control codes, which are implemented using an FPGA.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Single-Event Effect / ECC / Spotty byte error / Reed-Solomon code / encoder/decode circuit
Paper # SAT2005-57
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Committee SAT
Conference Date 2006/2/10(1days)
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Registration To Satellite Telecommunications (SAT)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Development of Test Circuit for Spotty Byte Error Control Codes
Sub Title (in English)
Keyword(1) Single-Event Effect
Keyword(2) ECC
Keyword(3) Spotty byte error
Keyword(4) Reed-Solomon code
Keyword(5) encoder/decode circuit
1st Author's Name Takeshi SASADA
1st Author's Affiliation Japan Aerospace Exploration Agency Tsukuba Space Center()
2nd Author's Name Haruhiko KANEKO
2nd Author's Affiliation Japan Aerospace Exploration Agency Tsukuba Space Center
3rd Author's Name Hideki IMASHIRO
3rd Author's Affiliation Hitachi Information Technology Co., Ltd.
Date 2006-02-17
Paper # SAT2005-57
Volume (vol) vol.105
Number (no) 605
Page pp.pp.-
#Pages 6
Date of Issue