Presentation | 2006/1/13 Practical FinFET Design Considering GIDL for LSTP Devices Katsuhiko TANAKA, Kiyoshi TAKEUCHI, Masami HANE, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Practical design of double-gate undoped-channel FinFET has been investigated through 3D device simulations considering gate-induced drain leakage (GIDL). Optimization of FinFET structure was carried out for hp45 low standby power (LSTP) device (L_g=25nm). GIDL is reduced by using gradual and offset source/drain (S/D) profile while degradation of drive current is minimized. Through the optimization of lateral spread and offset of S/D profile, the ITRS specifications for drive current and off-state leakage current are achievable. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | FinFET / double gate / GIDL / device simulation / LSTP |
Paper # | SDM2005-233 |
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Committee | SDM |
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Conference Date | 2006/1/13(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Silicon Device and Materials (SDM) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Practical FinFET Design Considering GIDL for LSTP Devices |
Sub Title (in English) | |
Keyword(1) | FinFET |
Keyword(2) | double gate |
Keyword(3) | GIDL |
Keyword(4) | device simulation |
Keyword(5) | LSTP |
1st Author's Name | Katsuhiko TANAKA |
1st Author's Affiliation | System Devices Res. Labs., NEC Corp.() |
2nd Author's Name | Kiyoshi TAKEUCHI |
2nd Author's Affiliation | System Devices Res. Labs., NEC Corp. |
3rd Author's Name | Masami HANE |
3rd Author's Affiliation | System Devices Res. Labs., NEC Corp. |
Date | 2006/1/13 |
Paper # | SDM2005-233 |
Volume (vol) | vol.105 |
Number (no) | 541 |
Page | pp.pp.- |
#Pages | 4 |
Date of Issue |