| Presentation | 2006-01-18 The direct execution mode on dynamically reconfigurable processors Hideharu AMANO, Yohei HASEGAWA, Shohei ABE, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Most of media processing consists of a sequence of multiple tasks. When it is executed on a dynamically reconfigurable processor, a heavy weight task with high degree of parallelism is selected and executed on the Processing Element (PE) array. Other light weight tasks with little processor are executed on the embedded processor so as not to waste the context memory. However, frequent data transfer between PE array and an embedded processor may degrade the performance and increase the consuming power. In order to solve the problem, the direct execution method in which a part of PEs execute configuration data transferred from the central configuration memory directly is proposed. In order to enhance the execution performance, the configuration template and the reconfigurable configuration mechanism are also proposed. Preliminarily evaluation demonstrates that the execution performance is comparable with a 2-way superscalar MIPS with 150MHz clock when the configuration data bus is stretched so as to configure two PEs simultaneously. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Reconfigurable Processor / DRP / Dynamic Reconfiguration |
| Paper # | VLD2005-99,CPSY2005-55,RECONF2005-88 |
| Date of Issue |
| Conference Information | |
| Committee | CPSY |
|---|---|
| Conference Date | 2006/1/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Computer Systems (CPSY) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | The direct execution mode on dynamically reconfigurable processors |
| Sub Title (in English) | |
| Keyword(1) | Reconfigurable Processor |
| Keyword(2) | DRP |
| Keyword(3) | Dynamic Reconfiguration |
| 1st Author's Name | Hideharu AMANO |
| 1st Author's Affiliation | Dept. of ICS, Keio University() |
| 2nd Author's Name | Yohei HASEGAWA |
| 2nd Author's Affiliation | Dept. of ICS, Keio University |
| 3rd Author's Name | Shohei ABE |
| 3rd Author's Affiliation | Dept. of ICS, Keio University |
| Date | 2006-01-18 |
| Paper # | VLD2005-99,CPSY2005-55,RECONF2005-88 |
| Volume (vol) | vol.105 |
| Number (no) | 516 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |