Presentation 2006-01-26
Silicon Nanodevices Based on SOI Structures Embedding an Artificial Dislocation Network
Yasuhiko ISHIKAWA, Chihiro YAMAMOTO, Michiharu TABE,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) Si single-electron devices using an artificial dislocation network are reported. A two-dimensional network of screw dislocations embedded in an SOI layer is successfully formed at the directly bonded interface between two commercially available SOI wafers. Formation of a periodic potential is expected in the SOI layer due to the change in the band edge energies induced by the strain field around the dislocations. In fact, metal-oxide-semiconductor field-effect transistors, embedding a dislocation network with the period of 20nm, show oscillatory drain current-gate voltage characteristics due to the single-electron tunneling. The result indicates that the dislocation network is effective to form the periodic potential in the SOI layer, which works as the multiple tunnel junctions.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) SOI / Artificial Dislocation Network / Direct Wafer Bonding / Single-Electron Tunneling / Periodic Potential / Multiple Tunnel Junctions
Paper # ED2005-224,SDM2005-236
Date of Issue

Conference Information
Committee ED
Conference Date 2006/1/19(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Electron Devices (ED)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Silicon Nanodevices Based on SOI Structures Embedding an Artificial Dislocation Network
Sub Title (in English)
Keyword(1) SOI
Keyword(2) Artificial Dislocation Network
Keyword(3) Direct Wafer Bonding
Keyword(4) Single-Electron Tunneling
Keyword(5) Periodic Potential
Keyword(6) Multiple Tunnel Junctions
1st Author's Name Yasuhiko ISHIKAWA
1st Author's Affiliation Research Institute of Electronics, Shizuoka University()
2nd Author's Name Chihiro YAMAMOTO
2nd Author's Affiliation Research Institute of Electronics, Shizuoka University
3rd Author's Name Michiharu TABE
3rd Author's Affiliation Research Institute of Electronics, Shizuoka University
Date 2006-01-26
Paper # ED2005-224,SDM2005-236
Volume (vol) vol.105
Number (no) 549
Page pp.pp.-
#Pages 6
Date of Issue