Presentation	2006-01-26 Low Leakage-power FPGA Design using Zigzag Power-gating, Dual V_	/V_ and Micro-V_ -Hopping Canh Quang TRAN, Hiroshi KAWAGUCHI, Takayasu SAKURAI,
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Abstract(in English)	Low-power FPGA architecture is proposed based on fine-grained V_ control scheme called micro-V_ -hopping. Four Configurable Logic Blocks (CLB) are grouped into one block where V_ is shared. In the micro-V_ -hopping scheme, V_ of each block is varied between the higher V_ (V_) and the lower V_ (V_) spatially and temporally to achieve lower power without performance degraded. A level shifter that has less contention is proposed. The FPGA also incorporates Zigzag power-gating scheme, special care has been taken to cope with sneak leakage path problem. To reduce power dissipated by interconnect, low swing interconnect is adopted. The proposed FPGA is fabricated using 0.35μm CMOS technology together with the conventional fixed-V_ FPGA. Measurement shows that the dynamic power can be reduced by 86% when the required speed is half of the maximum achievable speed. Simulation using 90nm CMOS technology shows that a leakage power reduction of 95% can be achieved, when the proposed method is used. Area overhead of the proposed FPGA is 2%.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	V_ hopping / Zigzag power-gating / low leakage power / low swing / sneak leakage current / FPGA
Paper #	ICD2005-208
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Conference Information
Committee	ICD
Conference Date	2006/1/19(1days)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Low Leakage-power FPGA Design using Zigzag Power-gating, Dual V_	/V_ and Micro-V_ -Hopping
Sub Title (in English)
Keyword(1)	V_ hopping
Keyword(2)	Zigzag power-gating
Keyword(3)	low leakage power
Keyword(4)	low swing
Keyword(5)	sneak leakage current
Keyword(6)	FPGA
1st Author's Name	Canh Quang TRAN
1st Author's Affiliation	Institute of Industrial Science, University of Tokyo()
2nd Author's Name	Hiroshi KAWAGUCHI
2nd Author's Affiliation	Department of Computer and Systems Engineering, Kobe University
3rd Author's Name	Takayasu SAKURAI
3rd Author's Affiliation	Institute of Industrial Science, University of Tokyo
Date	2006-01-26
Paper #	ICD2005-208
Volume (vol)	vol.105
Number (no)	569
Page	pp.pp.-
#Pages	6
Date of Issue