| Presentation | 2002/6/24 Double-Gate Poly-Si Thin-Film Transistors Fabricated Using Self-Aligned Technology Kenji MAKIHIRA, Kousuke NAKAGAWA, Tanemasa ASANO, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Double-gate TFTs having a buried bottom-gate were fabricated using a new self-aligned process. The photolithography for the top-gate was performed using the bottom-gate as the photo-mask and by exposing from the backside of the quartz wafer. We have been able to fabricate perfectly self-aligned double-gate TFTs using 4 photo-masks; bottom-gate, field isolation, contact hole and metalization. Drain current of about 3-fold the drain current of single-gate operation was obtained by double-gate operation. Current drive was also increased by thinning TFT active layer. The threshold voltage for the single-gate operation was able to be varied by changing the bias of the other gate. Uniformity in threshold voltage was improved by double-gate operation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | poly-Si / thin film transistor / double gate / self aligned technology |
| Paper # | ED2002-156 |
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| Conference Information | |
| Committee | ED |
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| Conference Date | 2002/6/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Electron Devices (ED) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Double-Gate Poly-Si Thin-Film Transistors Fabricated Using Self-Aligned Technology |
| Sub Title (in English) | |
| Keyword(1) | poly-Si |
| Keyword(2) | thin film transistor |
| Keyword(3) | double gate |
| Keyword(4) | self aligned technology |
| 1st Author's Name | Kenji MAKIHIRA |
| 1st Author's Affiliation | Center for Microelectronic Systems, Kyushu Institute of Technology() |
| 2nd Author's Name | Kousuke NAKAGAWA |
| 2nd Author's Affiliation | Center for Microelectronic Systems, Kyushu Institute of Technology |
| 3rd Author's Name | Tanemasa ASANO |
| 3rd Author's Affiliation | Center for Microelectronic Systems, Kyushu Institute of Technology |
| Date | 2002/6/24 |
| Paper # | ED2002-156 |
| Volume (vol) | vol.102 |
| Number (no) | 175 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |