| Presentation | 2002/6/24 Characterization and Simulation of Polycrystalline-Silicon Thin-Film Transistors Mutsumi KIMURA, Satoshi INOUE, Tatsuya SHIMODA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Characterization and simulation of polycrystalline-silicon thin-film transistors (poly-Si TFTs) are explained with some examples of their applications. For characterization, a technique to extract trap densities at oxide interfaces and grain boundaries has been developed. Actual trap densities are extracted, and degradation is analyzed. For device simulation, these trap states are implemented and carrier transport through grain boundaries is modeled. Dependence of transistor characteristics on these trap states is analyzed. For circuit simulation, a numerical model has been developed to reproduce transistor characteristics using experiments or the device simulation mentioned above. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Polycrystalline-Silicon / poly-Si / Thin-Film Transistor / TFT / Characterization / Simulation |
| Paper # | ED2002-151 |
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| Conference Information | |
| Committee | ED |
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| Conference Date | 2002/6/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Electron Devices (ED) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Characterization and Simulation of Polycrystalline-Silicon Thin-Film Transistors |
| Sub Title (in English) | |
| Keyword(1) | Polycrystalline-Silicon |
| Keyword(2) | poly-Si |
| Keyword(3) | Thin-Film Transistor |
| Keyword(4) | TFT |
| Keyword(5) | Characterization |
| Keyword(6) | Simulation |
| 1st Author's Name | Mutsumi KIMURA |
| 1st Author's Affiliation | Technology Platform Research Center, Seiko Epson Corporation() |
| 2nd Author's Name | Satoshi INOUE |
| 2nd Author's Affiliation | Technology Platform Research Center, Seiko Epson Corporation |
| 3rd Author's Name | Tatsuya SHIMODA |
| 3rd Author's Affiliation | Technology Platform Research Center, Seiko Epson Corporation |
| Date | 2002/6/24 |
| Paper # | ED2002-151 |
| Volume (vol) | vol.102 |
| Number (no) | 175 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |