Presentation 2002/6/24
Fabrication of SON(Silicon on Nothing)-MOSFET and Its ULSI Applications
Tsutomu SATO, Hideaki NII, Masayuki HATANO, Keiichi TAKENAKA, Hisataka HAYASHI, Kazutaka ISHIGO, Tomoyuki HIRANO, Kazuhiko IDA, Nobutoshi AOKI, Tatsuya OHGURO, Kazumi INO, Ichiro MIZUSHIMA, Yoshitaka TSUNASHIMA,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) A practical method for the formation of silicon on nothing (SON) structure with a desired size and shape has been developed, which is named as the empty space in silicon (ESS) technique. The concept of ESS technique and properties of SON structure fabricated by ESS technique are presented. SON-MOSFET was successfully fabricated for the first time by using ESS technique as an alternative of SOI-MOSFET. Advantage of SON structure was experimentally demonstrated. SON structure formed by ESS technique is appropriate for System on a Chip (SoC) applications, such as embedded trench DRAMs and digital-analog mixed devices, due to the merit that SON structure can be fabricated partially on bulk substrate.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) SON(Silicon on Nothing) / SOI(Silicon on Insulator) / ESS(Empty Space in Silicon) / silicon migration / hydrogen annealing
Paper # ED2002-138
Date of Issue

Conference Information
Committee ED
Conference Date 2002/6/24(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Electron Devices (ED)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Fabrication of SON(Silicon on Nothing)-MOSFET and Its ULSI Applications
Sub Title (in English)
Keyword(1) SON(Silicon on Nothing)
Keyword(2) SOI(Silicon on Insulator)
Keyword(3) ESS(Empty Space in Silicon)
Keyword(4) silicon migration
Keyword(5) hydrogen annealing
1st Author's Name Tsutomu SATO
1st Author's Affiliation Semiconductor Company TOSHIBA Corporation()
2nd Author's Name Hideaki NII
2nd Author's Affiliation Semiconductor Company TOSHIBA Corporation
3rd Author's Name Masayuki HATANO
3rd Author's Affiliation Semiconductor Company TOSHIBA Corporation
4th Author's Name Keiichi TAKENAKA
4th Author's Affiliation Semiconductor Company TOSHIBA Corporation
5th Author's Name Hisataka HAYASHI
5th Author's Affiliation Semiconductor Company TOSHIBA Corporation
6th Author's Name Kazutaka ISHIGO
6th Author's Affiliation Semiconductor Company TOSHIBA Corporation
7th Author's Name Tomoyuki HIRANO
7th Author's Affiliation Semiconductor Company TOSHIBA Corporation
8th Author's Name Kazuhiko IDA
8th Author's Affiliation Semiconductor Company TOSHIBA Corporation
9th Author's Name Nobutoshi AOKI
9th Author's Affiliation Semiconductor Company TOSHIBA Corporation
10th Author's Name Tatsuya OHGURO
10th Author's Affiliation Semiconductor Company TOSHIBA Corporation
11th Author's Name Kazumi INO
11th Author's Affiliation Semiconductor Company TOSHIBA Corporation
12th Author's Name Ichiro MIZUSHIMA
12th Author's Affiliation Semiconductor Company TOSHIBA Corporation
13th Author's Name Yoshitaka TSUNASHIMA
13th Author's Affiliation Semiconductor Company TOSHIBA Corporation
Date 2002/6/24
Paper # ED2002-138
Volume (vol) vol.102
Number (no) 175
Page pp.pp.-
#Pages 6
Date of Issue