| Presentation | 2002/6/24 An Effective Extraction of Distributed RLC Circuit Model for Multi-level Interconnects by Layout-Fracturing Algorithm Sukin YOON, Taeyoung WON, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we propose a layout-fracturing algorithm for the estimation of signal delay at multi-level interconnects. The proposed algorithm divides layout into three types of segments, electrical node segments, resistive segments and capacitive segments, for generation of a distributed RLC circuit model. The fractured segments are transferred directly into a complex RLC circuits by PEEC model, and these segments define each simulation domain and the boundary condition for extracting the parasitics in the distributed RLC network. In order to extract a set of resistance, inductance and capacitance, we solve Maxwell's Equation together with continuity equation over dielectrics and conductors medium using the finite element method (FEM). A sampler circuit, which has 24 transistors for a 3.3 V CMOS technology with 0.25 μm feature size, was examined for the application of our approach. In this work, the signal delay of 0.07 ns is induced by the conventional approach. According to our approach, however, signal operation has more signal delay of 0.17 ns. It increased 33% more than the result of the conventional approach. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Equivalent Circuit / Interconnect / Parasitics / Extraction / FEM |
| Paper # | ED2002-132 |
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| Committee | ED |
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| Conference Date | 2002/6/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Electron Devices (ED) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Effective Extraction of Distributed RLC Circuit Model for Multi-level Interconnects by Layout-Fracturing Algorithm |
| Sub Title (in English) | |
| Keyword(1) | Equivalent Circuit |
| Keyword(2) | Interconnect |
| Keyword(3) | Parasitics |
| Keyword(4) | Extraction |
| Keyword(5) | FEM |
| 1st Author's Name | Sukin YOON |
| 1st Author's Affiliation | School of Electronics and Electrical Engineering, Inha University() |
| 2nd Author's Name | Taeyoung WON |
| 2nd Author's Affiliation | School of Electronics and Electrical Engineering, Inha University |
| Date | 2002/6/24 |
| Paper # | ED2002-132 |
| Volume (vol) | vol.102 |
| Number (no) | 175 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |