Presentation 2002/6/24
Design and Fabrication of SiC RESURF MOSFETs
Hajime Kosugi, Taichi Hirao, Hiroshi Yano, Jun Suda, Tsunenobu Kimoto, Hiroyuki Matsunami,
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Abstract(in English) Design consideration and characteristics of the fabricated SiC RESURF MOSFETs are described. The RESURF (REduced SURface Field) structure is one of the most widely-used concepts for the design of lateral high-voltage devices, which are key components in power integrated circuits. The RESURF structure in SiC lateral MOSFETs was optimized by using a device simulator. Then RESURF MOSFETs were fabricated on 6H-SiC. A MOSFET exhibited the maximum breakdown-voltage of 700 V and the minimum specific on-resistance of 0.69 Ωcm^2.
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Keyword(in English) silicon carbide / power MOSFET / RESURF / simulation
Paper # ED2002-130
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Committee ED
Conference Date 2002/6/24(1days)
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Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design and Fabrication of SiC RESURF MOSFETs
Sub Title (in English)
Keyword(1) silicon carbide
Keyword(2) power MOSFET
Keyword(3) RESURF
Keyword(4) simulation
1st Author's Name Hajime Kosugi
1st Author's Affiliation Department of Electronic Science and Engineering, Kyoto University()
2nd Author's Name Taichi Hirao
2nd Author's Affiliation Department of Electronic Science and Engineering, Kyoto University
3rd Author's Name Hiroshi Yano
3rd Author's Affiliation Department of Electronic Science and Engineering, Kyoto University
4th Author's Name Jun Suda
4th Author's Affiliation Department of Electronic Science and Engineering, Kyoto University
5th Author's Name Tsunenobu Kimoto
5th Author's Affiliation Department of Electronic Science and Engineering, Kyoto University
6th Author's Name Hiroyuki Matsunami
6th Author's Affiliation Department of Electronic Science and Engineering, Kyoto University
Date 2002/6/24
Paper # ED2002-130
Volume (vol) vol.102
Number (no) 175
Page pp.pp.-
#Pages 5
Date of Issue