Presentation | 2002/6/24 DESIGN OF A 3V 6-BIT 900MSPS CMOS A/D CONVERTER WITH AN IMPROVED DYNAMIC LATCH Jinho Oh, Minkyu Song, |
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Abstract(in English) | A 3V 6-bit 900MSPS CMOS A/D Converter with an improved dynamic latch is proposed. It is composed of both a coarse ADC and a fine ADC whose FR(Folding Rate) is 2, NFB(Number of Folding Block) is 4, and IR(interpolation Rate) is 8, respectively. For the purpose of improving SNDR, distributed track-and-hold circuits are included at the input stage. In order to obtain a high-speed operation and low power consumption, further, a novel analog dynamic latch and digital encoder based on a fast compression algorithm are proposed. The chip has been fabricated with a 0.35um 2-poly 4-metal CMOS technology. The effective chip area is about 960um x 760um and it dissipates about 280mW at 3V power supply. The INL and DNL are within ±1LSB, respectively. The SNDR is about 31dB, when the input frequency reaches 40MHz at 900MHz clock frequency. |
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Paper # | ED2002-121 |
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Committee | ED |
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Conference Date | 2002/6/24(1days) |
Place (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Electron Devices (ED) |
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Language | ENG |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | DESIGN OF A 3V 6-BIT 900MSPS CMOS A/D CONVERTER WITH AN IMPROVED DYNAMIC LATCH |
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1st Author's Name | Jinho Oh |
1st Author's Affiliation | Dept. of Semiconductor Science, Dongguk University() |
2nd Author's Name | Minkyu Song |
2nd Author's Affiliation | Dept. of Semiconductor Science, Dongguk University |
Date | 2002/6/24 |
Paper # | ED2002-121 |
Volume (vol) | vol.102 |
Number (no) | 175 |
Page | pp.pp.- |
#Pages | 4 |
Date of Issue |