| Presentation | 2002/6/24 Effects of Fluorine Incorporation on the Negative-Bias-Temperature Instability (NBTI) of P-Channel MOSFETs Wan-Ju CHIANG, Da-Yuan LEE, Horng-Chih LIN, Wen-Tai LU, Tiao-Yuan HUANG, |
|---|---|
| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The impacts of fluorine incorporation on the characteristics of p^+-poly-Si-gated PMOSFETs were measured before and after negative-bias-temperature-instability (NBTI) stress. Fluorine species was incorporated during S/D extension and/or deep S/D implantation using BF_2^+. A reduction in interface state density with higher F dosage is observed. Moreover, the NBTI resistance is also found to increase with increasing F incorporation, as long as the thermal budget is carefully controlled to prevent the occurrence of boron penetration phenomenon. These improvements can be ascribed to the replacement of the bonded H atoms by F ones at the Si-SiO_2 interface. However, the threshold voltage as well as oxide thickness also varies with fluorine incorporation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | negative-bias-temperature-instability (NBTI) / PMOSFETs / Thin gate oxide |
| Paper # | ED2002-119 |
| Date of Issue |
| Conference Information | |
| Committee | ED |
|---|---|
| Conference Date | 2002/6/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Electron Devices (ED) |
|---|---|
| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Effects of Fluorine Incorporation on the Negative-Bias-Temperature Instability (NBTI) of P-Channel MOSFETs |
| Sub Title (in English) | |
| Keyword(1) | negative-bias-temperature-instability (NBTI) |
| Keyword(2) | PMOSFETs |
| Keyword(3) | Thin gate oxide |
| 1st Author's Name | Wan-Ju CHIANG |
| 1st Author's Affiliation | Institute of Electronics, National Chiao Tung University() |
| 2nd Author's Name | Da-Yuan LEE |
| 2nd Author's Affiliation | Institute of Electronics, National Chiao Tung University |
| 3rd Author's Name | Horng-Chih LIN |
| 3rd Author's Affiliation | National Nano Device Laboratories |
| 4th Author's Name | Wen-Tai LU |
| 4th Author's Affiliation | Institute of Electronics, National Chiao Tung University |
| 5th Author's Name | Tiao-Yuan HUANG |
| 5th Author's Affiliation | Institute of Electronics, National Chiao Tung University:National Nano Device Laboratories |
| Date | 2002/6/24 |
| Paper # | ED2002-119 |
| Volume (vol) | vol.102 |
| Number (no) | 175 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |