講演名 | 2002/6/24 A new DRAM Cell for SoC (System on a Chip) Devices : Planar DRAM Cell, Based On Logic Process , |
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抄録(英) | A new DRAM Cell for SoC (System on a Chip) Devices is introduced and discussed. An improvement in electrical characteristics of DRAM Cell is obtained by PMOS type cell instead of NMOS. It is of DRAM Cell's leakage currents. The leakage currents are related to data retention time. The PMOS DRAM Cell also results in lower capacitance and lower tr. performance. However, the good data retention time may outweigh the disadvantages and can significantly improve DRAM characteristics in SoC Product. For the substrate (N-Well) bias condition of PMOS DRAM Cell higher than operating voltage (Vcc), it is good immunity for noises and voltage's bouncing on a chip level. This detailed study shows that the PMOS DRAM Cell has several unique advantages over the NMOS DRAM Scheme such as a small cell tr. leakage current and cell capacitor's leakage. Also, it is suitable for high-performance logic devices included in DRAM's. |
キーワード(和) | |
キーワード(英) | SoC(System on a Chip) / DRAM Cell / Logic Device |
資料番号 | ED2002-117 |
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研究会情報 | |
研究会 | ED |
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開催期間 | 2002/6/24(から1日開催) |
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講演論文情報詳細 | |
申込み研究会 | Electron Devices (ED) |
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本文の言語 | ENG |
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サブタイトル(和) | |
タイトル(英) | A new DRAM Cell for SoC (System on a Chip) Devices : Planar DRAM Cell, Based On Logic Process |
サブタイトル(和) | |
キーワード(1)(和/英) | / SoC(System on a Chip) |
第 1 著者 氏名(和/英) | / Seoyong CHI |
第 1 著者 所属(和/英) | System IC R&D Center, Hynix Semiconductor Inc. |
発表年月日 | 2002/6/24 |
資料番号 | ED2002-117 |
巻番号(vol) | vol.102 |
号番号(no) | 175 |
ページ範囲 | pp.- |
ページ数 | 3 |
発行日 |