| Presentation | 2002/6/24 A new DRAM Cell for SoC (System on a Chip) Devices : Planar DRAM Cell, Based On Logic Process Seoyong CHI, Jeongho CHO, Yongcheol JEONG, Choongho HWANG, Junghwan LEE, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A new DRAM Cell for SoC (System on a Chip) Devices is introduced and discussed. An improvement in electrical characteristics of DRAM Cell is obtained by PMOS type cell instead of NMOS. It is of DRAM Cell's leakage currents. The leakage currents are related to data retention time. The PMOS DRAM Cell also results in lower capacitance and lower tr. performance. However, the good data retention time may outweigh the disadvantages and can significantly improve DRAM characteristics in SoC Product. For the substrate (N-Well) bias condition of PMOS DRAM Cell higher than operating voltage (Vcc), it is good immunity for noises and voltage's bouncing on a chip level. This detailed study shows that the PMOS DRAM Cell has several unique advantages over the NMOS DRAM Scheme such as a small cell tr. leakage current and cell capacitor's leakage. Also, it is suitable for high-performance logic devices included in DRAM's. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SoC(System on a Chip) / DRAM Cell / Logic Device |
| Paper # | ED2002-117 |
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| Conference Information | |
| Committee | ED |
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| Conference Date | 2002/6/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Electron Devices (ED) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A new DRAM Cell for SoC (System on a Chip) Devices : Planar DRAM Cell, Based On Logic Process |
| Sub Title (in English) | |
| Keyword(1) | SoC(System on a Chip) |
| Keyword(2) | DRAM Cell |
| Keyword(3) | Logic Device |
| 1st Author's Name | Seoyong CHI |
| 1st Author's Affiliation | System IC R&D Center, Hynix Semiconductor Inc.() |
| 2nd Author's Name | Jeongho CHO |
| 2nd Author's Affiliation | System IC R&D Center, Hynix Semiconductor Inc. |
| 3rd Author's Name | Yongcheol JEONG |
| 3rd Author's Affiliation | System IC R&D Center, Hynix Semiconductor Inc. |
| 4th Author's Name | Choongho HWANG |
| 4th Author's Affiliation | System IC R&D Center, Hynix Semiconductor Inc. |
| 5th Author's Name | Junghwan LEE |
| 5th Author's Affiliation | System IC R&D Center, Hynix Semiconductor Inc. |
| Date | 2002/6/24 |
| Paper # | ED2002-117 |
| Volume (vol) | vol.102 |
| Number (no) | 175 |
| Page | pp.pp.- |
| #Pages | 3 |
| Date of Issue | |