| Presentation | 2002/6/24 FEOL Process for Sub-100nm DRAM Gyoyoung Jin, Siyoung Choi, Jinhwa Heo, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Key technologies in front end of line (FEOL) process of DRAM for sub-100nm node generation are reviewed. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | DRAM / shallow trench isolation / tungsten gate / cobalt silicide |
| Paper # | ED2002-116 |
| Date of Issue |
| Conference Information | |
| Committee | ED |
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| Conference Date | 2002/6/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Electron Devices (ED) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | FEOL Process for Sub-100nm DRAM |
| Sub Title (in English) | |
| Keyword(1) | DRAM |
| Keyword(2) | shallow trench isolation |
| Keyword(3) | tungsten gate |
| Keyword(4) | cobalt silicide |
| 1st Author's Name | Gyoyoung Jin |
| 1st Author's Affiliation | DRAM PA() |
| 2nd Author's Name | Siyoung Choi |
| 2nd Author's Affiliation | Process Development Team,Semiconductor R&D Center Memory Division, Samsung Electronics Co. |
| 3rd Author's Name | Jinhwa Heo |
| 3rd Author's Affiliation | Process Development Team,Semiconductor R&D Center Memory Division, Samsung Electronics Co. |
| Date | 2002/6/24 |
| Paper # | ED2002-116 |
| Volume (vol) | vol.102 |
| Number (no) | 175 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |