Presentation 2002/4/5
SESO : Scalable Memory Using Ultra-thin Polycrystalline Silicon
Tomoyuki ISHI, Taro OSABE, Toshiyuki MINE, Fumio MURAI, Kazuo YANO,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) SE SO memory, which has potential to achieve low power, high density embedded memory without special materials, is proposed. By using ultra -thin polycrystalline silicon channel TFT, the leakage current becomes lower than that of standard bulk MOS transistor. A memory storing much lower charge than conventional DRAM can be operated by employing the TFT. Ultra low 1 eakage current of SE SO transistor and basic operations of SE SO memory are confirmed experimentally.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Embedded Memory / Low Power / TFT
Paper # ICD2002-14
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Committee ICD
Conference Date 2002/4/5(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) SESO : Scalable Memory Using Ultra-thin Polycrystalline Silicon
Sub Title (in English)
Keyword(1) Embedded Memory
Keyword(2) Low Power
Keyword(3) TFT
1st Author's Name Tomoyuki ISHI
1st Author's Affiliation Hitachi Central Research Laboratory()
2nd Author's Name Taro OSABE
2nd Author's Affiliation Hitachi Central Research Laboratory
3rd Author's Name Toshiyuki MINE
3rd Author's Affiliation Hitachi Central Research Laboratory
4th Author's Name Fumio MURAI
4th Author's Affiliation Hitachi Central Research Laboratory
5th Author's Name Kazuo YANO
5th Author's Affiliation Hitachi Central Research Laboratory
Date 2002/4/5
Paper # ICD2002-14
Volume (vol) vol.102
Number (no) 3
Page pp.pp.-
#Pages 3
Date of Issue