Presentation 2002/4/5
Impact of Lower Dot Size Scaling on Charge Retention in Doubly Stacked Si Dot Memory
Ryuji Ohba, Naoharu Sugiyama, Junji Koga, Ken Uchida,
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Abstract(in English) The quantum dot memory, whose floating gate consists of doubly stacked Si dots, can attain excellent charge retention, keeping a high-speed write/erase (w/e). This is because Coulomb blockade and quantum confinement in a lower dot suppress charge leak between upper dot and channel effectively in low gate voltage (retention state), while such suppression disappears in high gate voltage (w/e state). Since the charge retention is improved exponentially by lower dot size scaling, Si double dot memory is a strong candidate for future low-voltage non-volatile memory.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Si dot / Double dot / Non-volatile memory / Coulomb blockade / Quantum confinement
Paper # ICD2002-12
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Committee ICD
Conference Date 2002/4/5(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Impact of Lower Dot Size Scaling on Charge Retention in Doubly Stacked Si Dot Memory
Sub Title (in English)
Keyword(1) Si dot
Keyword(2) Double dot
Keyword(3) Non-volatile memory
Keyword(4) Coulomb blockade
Keyword(5) Quantum confinement
1st Author's Name Ryuji Ohba
1st Author's Affiliation Advanced LSI Technology Laboratory, Toshiba Corporation()
2nd Author's Name Naoharu Sugiyama
2nd Author's Affiliation Advanced LSI Technology Laboratory, Toshiba Corporation
3rd Author's Name Junji Koga
3rd Author's Affiliation Advanced LSI Technology Laboratory, Toshiba Corporation
4th Author's Name Ken Uchida
4th Author's Affiliation Advanced LSI Technology Laboratory, Toshiba Corporation
Date 2002/4/5
Paper # ICD2002-12
Volume (vol) vol.102
Number (no) 3
Page pp.pp.-
#Pages 6
Date of Issue