Presentation 2002/4/5
Development of Nonvolatile Logic with Ferroelectric Capacitors
Yoshikazu FUJIMORI, Takashi NAKAMURA, Hidemi TAKASU,
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Abstract(in English) A Novel nonvolatile latch with ferroelectric capacitors has been developed to reduce standby power of LSIs. This latch stores the data as a ferroelectric remanent polarization during power off without the area penalty and the operating speed degradation. Test circuit have been fabricated to confirm characteristics of the latch. The data retention and the stable recall procedure have been confirmed. This paper also describes scalling projection of this technique.
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Keyword(in English) Ferroelectric / Logic / Latch / Low power / Low standby / MT-CMOS
Paper # ICD2002-10
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Committee ICD
Conference Date 2002/4/5(1days)
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Paper Information
Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Development of Nonvolatile Logic with Ferroelectric Capacitors
Sub Title (in English)
Keyword(1) Ferroelectric
Keyword(2) Logic
Keyword(3) Latch
Keyword(4) Low power
Keyword(5) Low standby
Keyword(6) MT-CMOS
1st Author's Name Yoshikazu FUJIMORI
1st Author's Affiliation Semiconductor Device R&D Div., ROHM Co., Ltd.()
2nd Author's Name Takashi NAKAMURA
2nd Author's Affiliation Semiconductor Device R&D Div., ROHM Co., Ltd.
3rd Author's Name Hidemi TAKASU
3rd Author's Affiliation Semiconductor Device R&D Div., ROHM Co., Ltd.
Date 2002/4/5
Paper # ICD2002-10
Volume (vol) vol.102
Number (no) 3
Page pp.pp.-
#Pages 6
Date of Issue