| Presentation | 2002/4/5 Design of Ferroelectric-Based Logic-in-Memory VLSI Hiromitsu KIMURA, Takahiro HANYU, Michitaka KAMEYAMA, Yoshikazu FUJIMORI, Takashi NAKAMURA, Hidemi TAKASU, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A ferroelectric-based logic-in-memory VLSI is proposed to implement a highly-parallel VLSI processor compactly. Since the state-transition scheme of remnant polarization in a ferroelectric capacitor is utilized to perform switching functions, the storage and switching function is merged into a ferroelectric capacitor. The use of a proposed circuit makes it possible to distribute a high-speed storage elements over logic-circuit plane with a small area overhead. As a typical example, a 250MHz 54×54-bit pipelined multiplier is demonstrated with 7.82mm^2 estimated area in a 0.6μm ferroelectric/CMOS technology. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Ferroelectric capacitor / functional pass-gate / pass-transistor network / fine-grain pipelined system |
| Paper # | ICD2002-9 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2002/4/5(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design of Ferroelectric-Based Logic-in-Memory VLSI |
| Sub Title (in English) | |
| Keyword(1) | Ferroelectric capacitor |
| Keyword(2) | functional pass-gate |
| Keyword(3) | pass-transistor network |
| Keyword(4) | fine-grain pipelined system |
| 1st Author's Name | Hiromitsu KIMURA |
| 1st Author's Affiliation | Graduate School of Information Sciences, Tohoku University() |
| 2nd Author's Name | Takahiro HANYU |
| 2nd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| 3rd Author's Name | Michitaka KAMEYAMA |
| 3rd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| 4th Author's Name | Yoshikazu FUJIMORI |
| 4th Author's Affiliation | Device Technology Div., Semiconductor R&D Headquarters, Rohm Co.,ltd. |
| 5th Author's Name | Takashi NAKAMURA |
| 5th Author's Affiliation | Device Technology Div., Semiconductor R&D Headquarters, Rohm Co.,ltd. |
| 6th Author's Name | Hidemi TAKASU |
| 6th Author's Affiliation | Device Technology Div., Semiconductor R&D Headquarters, Rohm Co.,ltd. |
| Date | 2002/4/5 |
| Paper # | ICD2002-9 |
| Volume (vol) | vol.102 |
| Number (no) | 3 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |