Presentation 2002/4/12
Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method
Yusuke OGURO, Tomohiro YONEDA,
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Abstract(in English) Using a level oriented model for verification of asynchronous circuits helps users to easily construct formal models with high readability or to naturally model data-path circuits. On the other hand, in order to use such a model for a little larger circuit, some technique to avoid the state explosion problem is essential. This paper first defines one level oriented formal model based on time Petri nets, and then proposes its partial order reduction algorithm that prunes unnecessary state generation with guaranteeing the correctness of the verification.
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Keyword(in English) Level oriented model / asynchronous circuits / formal verification / time Petri nets.
Paper # DC2002-7
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Conference Date 2002/4/12(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method
Sub Title (in English)
Keyword(1) Level oriented model
Keyword(2) asynchronous circuits
Keyword(3) formal verification
Keyword(4) time Petri nets.
1st Author's Name Yusuke OGURO
1st Author's Affiliation Graduate School of Information Science and Engineering, Tokyo Institute of Technology()
2nd Author's Name Tomohiro YONEDA
2nd Author's Affiliation Graduate School of Information Science and Engineering, Tokyo Institute of Technology
Date 2002/4/12
Paper # DC2002-7
Volume (vol) vol.102
Number (no) 28
Page pp.pp.-
#Pages 6
Date of Issue