講演名 | 2005-12-02 A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits , |
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抄録(和) | |
抄録(英) | This paper presents a broadside test generation method for transition faults in partial scan circuits. In order to generate broadside transition tests for a given partial scan circuit whose kernel circuit is acyclic, this method transforms the kernel circuit into some combinational circuits called broadside test generation models. These models are constructed by using a time-expansion model of the kernel circuit. All the broadside transition tests are generated by performing constrained stuck-at test generation on the broadside test generation models. This method is effective in terms of over-testing as well as area overhead compared with enhanced scan testing and broadside testing based on full scan technique. Experimental results show that the proposed method can alleviate the over-testing issue in reasonable test generation time. |
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キーワード(英) | transition fault / broadside test / broadside test generation model / constrained stuck-at test generation / over-testing |
資料番号 | VLD2005-77,ICD2005-172,DC2005-54 |
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研究会情報 | |
研究会 | VLD |
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開催期間 | 2005/11/25(から1日開催) |
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講演論文情報詳細 | |
申込み研究会 | VLSI Design Technologies (VLD) |
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本文の言語 | ENG |
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サブタイトル(和) | |
タイトル(英) | A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits |
サブタイトル(和) | |
キーワード(1)(和/英) | / transition fault |
第 1 著者 氏名(和/英) | / Tsuyoshi IWAGAKI |
第 1 著者 所属(和/英) | School of Information Science, Japan Advanced Institute of Science and Technology |
発表年月日 | 2005-12-02 |
資料番号 | VLD2005-77,ICD2005-172,DC2005-54 |
巻番号(vol) | vol.105 |
号番号(no) | 443 |
ページ範囲 | pp.- |
ページ数 | 6 |
発行日 |