Presentation 2005-12-02
A Logic Simulation using an Look-Up Table Cascade Emulator
Hiroki NAKAHARA, Tsutomu SASAO, Munehiro MATSUURA,
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Abstract(in English) This paper shows a cycle-based logic simulation method using an LUT cascade emulator. The LUT cascade emulator is an architecture that emulates LUT cascades, where multiple-output LUTs (cells) are connected in series. The LUT cascade emulator has a control part, a large memory, and registers. It connects the memory to each register by a programmable interconnection circuit, and evaluates the given circuit stored in the memory. This method realizes the LUT cascade emulator on a PC by a software. Experimental results show that this method is 18-2621 times faster than the LCC.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) BDD_for_CF / Functional decomposition / LUT cascade
Paper # VLD2005-85,ICD2005-180,DC2005-62
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Conference Date 2005/11/25(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Logic Simulation using an Look-Up Table Cascade Emulator
Sub Title (in English)
Keyword(1) BDD_for_CF
Keyword(2) Functional decomposition
Keyword(3) LUT cascade
1st Author's Name Hiroki NAKAHARA
1st Author's Affiliation Program of Creation Informatics, Kyushu Institute of Technology()
2nd Author's Name Tsutomu SASAO
2nd Author's Affiliation Department of Comoputer Science and Eloctronics, Kyushu Institute of Technology
3rd Author's Name Munehiro MATSUURA
3rd Author's Affiliation Department of Comoputer Science and Eloctronics, Kyushu Institute of Technology
Date 2005-12-02
Paper # VLD2005-85,ICD2005-180,DC2005-62
Volume (vol) vol.105
Number (no) 446
Page pp.pp.-
#Pages 6
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